A PLL is an important and widely used electronic component. Broadly speaking, a PLL includes a circuit for synchronizing an output signal with an input signal (also often referred to as a reference signal or the reference clock signal) in terms of frequency and/or phase. When the reference signal and the output signal are synchronized, they may be referred to as being locked.
One conventional PLL typically includes a voltage or current controlled oscillator (VCO, ICO) to generate the output signal in response to the reference signal. In addition, a feedback signal related to the output signal is provided to the PLL as another input. The feedback mechanism of the PLL generally tries to make the feedback signal look like the reference signal in time. In particular, the PLL typically adjusts itself to make the rise in edges of the feedback signal and the reference signal occur substantially together.
One common application of PLLs is in data input/output (I/O). Typically, a clock signal and some data are received at an I/O interface. In order to properly strobe or sample the data, the clock signal has to be appropriately lined up with the data. To do so, the I/O interface may use a conventional PLL to adjust the phase of the clock signal received. In addition, the I/O interface may include one or more dividers to increase the frequency of the clock signal. Generally speaking, the phase (⊖) of an output signal of the conventional PLL is related to the angular frequency (ω) of the VCO by: ⊖=ω*t, where t is time. For t=a time period (T) of the output signal, ⊖=2π. Thus, the conventional PLL may adjust the clock signal by 2π readily.
However, it is generally difficult for the conventional PLL to adjust the clock signal more finely, such as by increments less than the time period (T) of the output signal. Although one conventional approach is to run the VCO within the PLL faster in order to achieve a finer adjustment in phase, this approach generally requires more power, and may be further limited by the maximum speed the dividers or the VCO can run.
Another conventional approach is to bring out many phases of the VCO and then tap an output out of a number of outputs through different phases. Note that the outputs are phase related. However, this approach heavily depends on process matching of various components within the VCO, tapping structure, etc., over process, voltage and temperature, such mismatch becomes more significant as the VCO gets faster or the number of phases gets larger.
Alternatively, another conventional approach is to add delay blocks to the PLL in relation to the period of the VCO. However, this approach also suffers the same disadvantage of being heavily dependent on process matching. Generally, the delay blocks do not match very well. Furthermore, it is cumbersome to add many delay blocks to the PLL.